In NAND flash memories, a chip stack technology for stacking chips and accommodating them in one package has been conventionally adopted. In this technology, the chips are arranged in a staircase pattern, and these chips are connected to a package substrate or a lead frame by wire bonding.
In recent years, for the purpose of increasing a chip size that enables accommodation in a package or improving characteristics of a device, vertically stacking chips is examined. In this case, since a position of a terminal connected with each chip is the same in the stacked chips, how the stacked chips are decoded and selected is a subject. Therefore, a semiconductor device that enables selecting stacked chips is demanded.